1. Field of the Invention
The present invention generally relates to computer systems. More specifically, the present invention relates to a computer circuit for maximizing set up and hold time for data received from a double-data-rate synchronous memory device.
2. Description of the Related Art
Speed has always been an important factor in measuring the performance of a computer system, and speed depends, among other factors, how fast can data be retrieved from data registers for the central processing unit (CPU)'s use and how fast can data be stored into the data registers after CPU's calculation.
Data are stored into the data registers or memory locations with help of a strobe signal. The data can be latched to their location by either the rising edge or the falling edge of the strobe signal. To achieve a high data rate Double-Data-Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM or DDR) has been used. DDR differs from standard DRAM (or SDRAM) in that it uses a separate strobe signal by which some or all of its data timing is referenced and both the rising and the falling edges of the strobe signal are used to clock data into their destination. Thus, doubling the amount of data transferred in a given time interval. This technique also allows higher data rates than standard single-data-rate SDRAM because the explicit strobe signal by which data is referenced can be used to remove some of the timing uncertainty present in the receive path.
However, DDR-SDRAM presents challenges when interfacing to high-speed synchronous systems, and the challenges are related to data interface. The two different timing challenges are: (1) Aligning each strobe edge such that setup and hold timing margins at the receiving data latches are maximized. If the setup and hold timing margins are insufficient, the data retrieved or stored may not be accurate. The alignment of strobe edge is complicated by the fact that clock speeds have increased and the uncertainties associated with DDR-SDRAM read data timing have not scaled accordingly. For a clock period of 4 nanoseconds, a memory device may require one nanosecond setup time and one nanosecond hold time, thus yielding a two nanoseconds data window for the memory device. As the clock speed increases, the memory devices' requirement for time to read and write data has not relented. For a 1.5 nanosecond clock period, a memory device may require half nanosecond set up time and half nanosecond for hold time, thus leaving only a half nanosecond data window for the memory device. This has resulted in a disproportionate shrinkage of the valid data window, requiring more precise control of strobe timing positioning on its data; and (2) presenting the received data to its destination latch with no cycle-to-cycle ambiguity. At high clock speeds where timing uncertainty approaches an entire clock cycle, the cycle-to-cycle match is difficult.
Presenting the received data (read timing) is especially troublesome because a significant delay usually exists from the time that the system transitions the clock to a DDR part to the time that the data and its accompanying strobe edge arrive back at the system. The timing uncertainty in this path is usually large, in some cases as large as a DDR clock cycle. In most system designs, the received data must be presented to logic that is synchronous with the DDR clock.
Timing uncertainty may also be affected by environmental factors such as operating temperature and operating voltage. A clock period may change slightly from when the system is first booted to when the system reaches its operating temperature. Further, a change in operating voltage may also affect when a signal becomes active.
It would be advantageous for a system including a DDR-SDRAM to minimize timing uncertainty that can lead to ambiguity as to when a particular datum is available from a DDR-SDRAM, as well as minimize other timing-related problems such as setup and hold timing violations on clock-synchronous registers that follow registers clocked by the received strobes. It is to such a system and method the present invention is primarily directed.